(DELAYFILE (SDFVERSION "2.1") //版本信息 (DESIGN "test") //设计工程名称 (DATE "Sun Mar 23 13:29:07 2008") //日期 (VENDOR "ACTEL") //厂商 (PROGRAM "Actel Designer Software, Release v8.1 Copyright (C) 1989-2007 Actel Corp. ") (VERSION "8.1.0.32") (DIVIDER /) (VOLTAGE 1.58:1.50:1.43) (PROCESS "best:nom:worst") (TEMPERATURE 0:25:70) //温度范围 (TIMESCALE 100ps) //时间标度为100Ps
(CELL (CELLTYPE "AX1C") //模块名称 (INSTANCE q_n4) (DELAY //类型为delay,表明以下信息包含delay信息 (ABSOLUTE (PORT A (5.14:6.23:6.81) (4.89:5.93:6.48)) //走线延时 (IOPATH A Y (3.57:6.24:7.05) (3.29:4.14:4.67))//cell延时 (PORT B (7.32:8.88:9.70) (6.66:8.08:8.82)) (IOPATH B Y (3.65:6.42:7.24) (3.45:4.42:4.98)) (PORT C (1.80:2.18:2.38) (1.73:2.10:2.30)) (IOPATH C Y (1.85:3.23:3.65) (2.14:2.68:3.02)) ) ) )
可以看到PORT A中的延时值有两组，没组有三个值，最全的延时值应该有六组分别是0-1, 1-0, 0-Z, Z-1, 1-Z, Z-0, 0-X, X-1, 1-X, X-0, X-Z, Z-X，如果只有两组被声明，一组就是0-1，0-z,0-x，一组就是1-0，1-z,1-x
上例中即是这种例子。
IOPATH描述的延时是一个模块的输入端口到输出端口的延时
PORT描述的是内部走线的延时相对于输入端口的延时
(CELL (CELLTYPE "DFN1C1") (INSTANCE q\[1\]) (DELAY (ABSOLUTE (PORT D (1.85:2.24:2.45) (1.79:2.17:2.37)) (PORT CLK (5.92:7.18:7.84) (5.53:6.71:7.33)) (IOPATH CLK Q (2.84:3.48:3.93) (3.52:4.32:4.88)) (PORT CLR (8.33:10.10:11.03) (7.89:9.57:10.45)) (IOPATH CLR Q () (2.87:3.53:3.99)) ) ) (TIMINGCHECK (SETUP (posedge D) (posedge CLK) (3.84:4.72:5.32)) (SETUP (negedge D) (posedge CLK) (3.84:4.72:5.32)) (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00)) (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00)) (WIDTH (posedge CLK) (2.80:3.22:3.22)) (WIDTH (negedge CLK) (3.10:3.56:3.56)) (WIDTH (posedge CLR) (1.92:2.21:2.21)) (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22)) (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00)) ) )
TimingCheck： (SETUP (posedge D) (posedge CLK) (3.84:4.72:5.32)) D的上升沿和CLK上升沿最短时5.32（100ps单位）
(WIDTH (posedge CLK) (2.80:3.22:3.22)) 从CLK的下降沿算起到下一个CLK上升沿，最短时间不短于2.8
最小时钟脉宽（低电平），虽然最短脉宽这么短，但ACTEL内核频率不能超过350Mhz
SDF文件有有一些常见的时序检查，如 $hold $setup $nochange $setuphold $period $skew $recovery $width
例子1：
# ** Error:/path/to/xilinx/verilog/src/simprims/X_RAMD16.v(96):
$setup(negedge WE:29138 ps, posedge CLK:29151 ps, 373 ps);
# Time:29151 ps Iteration:0 Instance: /test_bench/u1/\U1/X_RAMD16\
1.setup表明这是建立时间的违例
2.negedge WE:29138 ps表明WE在29138ps处有一个下降沿的跳变
3.posedge CLK:29151 ps表明CLK在29151cps处有个上升沿的跳变
4.373ps表明在clk上升沿前，WE必须稳定的时间是373ps,但事实上只有13ps,违例。
例子2：
$Width Violations
查询一个信号的脉宽是否在规定的值范围内
$Recovery Violations
检查两个异步信号的时序关系，如检查一个寄存器的clr和CLK信号的时序关系，如果clr和clk变化太相近，系统就不知道到底是要锁存D上的这个信号还是不锁存。 文章来源： http://bbs.ednchina.com/BLOG_ARTICLE_98585.HTM
转载于:https://www.cnblogs.com/lmeqs/p/4312554.html
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