library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; subtype slv is std_logic_vector; signal dpll_counter : std_logic_vector( 4 downto 0 ); dpll_counter <= dpll_counter + "00001"; dpll_counter <= unsigned(dpll_counter) + 1; dpll_counter <= std_logic_vector( UNSIGNED(dpll_counter) + 1 ); dpll_counter <= slv( unsigned(dpll_counter) + 1 ); signal count : unsigned(input'range);count <= unsigned(input);count <= count + 1;output <= slv(count);Or define count as a natural: signal input, output : std_logic_vector( 4 downto 0);signal count : natural range 0 to 2**input'length-1;count <= count + 1; -- much faster rtl simulationoutput <= slv(to_unsigned(count, output'length));count <= to_integer(unsigned(input)); signal count : natural range 0 to 2**numbits-1; -- numbits wide count Thus count - 1 < 0 is still possible, even though count < 0 is not.This is an easy way to extract the carry condition in a down counter:if count - 1 < 0 then -- carry bit set count <= start_value; -- reloadelse count <= count - 1; -- updateend if; The synthesizer (XST, Quartus, Synplify-Pro, Precision, even the oldsynopsys DCFPGA) will automatically share the decrement between thecomparison and the update, and use the next bit (the sign bit) tocontrol the reload or update.The same sort of trick works for overflow in an up counter too. So I synthesized a couple versions to see what XST (ISE8.2) does (intoan XC2VP7), checking the results with fpga_editor. I first had to usefairly large counters or it would not necessarily use the carry chain,and I wanted to see how that was used.So the above mentioned:if count - 1 < 0 then -- carry bit setcount <= start_value; -- reloadelsecount <= count - 1; -- updateend if;That created two parallel sets of LUTs, one with the counter itself, andone that simply calculates count-1 using a carry chain. It is the carryoutput of this second chain that triggers reloading of the counter.Next:if count = 0 then -- carry bit setcount <= start_value; -- reloadelsecount <= count - 1; -- updateend if;That created a single chain for the counter, and then in LUTs itimplemented ~count1*~count2*~count3... , with the output of thattriggering the load.The second method actually uses less logic than the first, but neitherwas ideal. I must say, I am not impressed with XST synthesis ofsomething so basic as a counter :-( In the numeric_std package there is a type called "unsigned" (andanother called "signed") for doing math. This allows you keep theconcept of a signed and unsigned number separate. You would do it likethis:signal count : unsigned ( 7 downto 0);....count <= count + 1;If you really need it in std_logic_vector you can say:countslv <= std_logic_vector (count);
转载于:https://www.cnblogs.com/shangdawei/archive/2011/01/25/1944813.html
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