1 -- =============================================================================
2 --
file name
is: mux4_1.vhd (mux=
multiplexer)
3 --
Author: Kim Petersen
4 -- Created:
00.04.
10 last modified:
00.04.
13
5 -- =============================================================================
6 -- It
is a
4 input multiplexer
with the
function as:
7 -- sel Input =>
output comments
8 --
MSB LSB
9 --
0 0 in0 =>
output
10 --
0 1 in1 =>
output
11 --
1 0 in2 =>
output
12 --
1 1 in3 =>
output
13 --
14 --------
15 --
IF and CASE can only be used inside a
process.
16 --
WHEN and WITH can only be used outside a
process.
17 --
18 --
IF corresponds
to WHEN
19 --
CASE correpsonds
to WITH
20 -- =============================================================================
21
22 library ieee;
23 use ieee.std_logic_1164.
all; -- can be different dependent
on tool used.
24 use ieee.std_logic_unsigned.
all; -- can be different dependent
on tool used.
25
26 entity mux4_1
is
27 port (s0 :
in STD_LOGIC;
28 s1 :
in STD_LOGIC;
29 in0 :
in STD_LOGIC;
30 in1 :
in STD_LOGIC;
31 in2 :
in STD_LOGIC;
32 in3 :
in STD_LOGIC;
33 output :
out STD_LOGIC
34 );
35 end mux4_1;
36 -- =============================================================================
37 -- =============================================================================
38 architecture if_example
of mux4_1
is
39
40 -- =============================================================================
41 begin
42
43 mux :
process(s0, s1, in0, in1, in2, in3)
44 begin
45
46 if (s0 =
'0' and s1 =
'0')
then
47 output <=
in0;
48 elsif (s0 =
'1' and s1 =
'0')
then
49 output <=
in1;
50 elsif (s0 =
'0' and s1 =
'1')
then
51 output <=
in2;
52 elsif (s0 =
'1' and s1 =
'1')
then
53 output <=
in3;
54 else -- (s0
or s1 are
not 0 or 1)
55 output <=
'X';
56 end if;
57
58 end process mux;
59
60 end if_example;
61
62 -- =============================================================================
63 -- =============================================================================
64 architecture case_example
of mux4_1
is
65
66 -- =============================================================================
67 begin
68
69 mux :
process(s0, s1, in0, in1, in2, in3)
70 variable sel :
STD_LOGIC_VECTOR(
1 downto 0);
71 begin
72 sel := s1 & s0; -- concatenate s1
and s0
73
74 case sel
is
75 when "00" =>
output <=
in0;
76 when "01" =>
output <=
in1;
77 when "10" =>
output <=
in2;
78 when "11" =>
output <=
in3;
79 when others =>
output <=
'X';
80 end case;
81
82 end process mux;
83
84 end case_example;
85
86 -- =============================================================================
87 -- =============================================================================
88 architecture with_example
of mux4_1
is
89
90 signal sel :
STD_LOGIC_VECTOR(
1 downto 0);
91 -- =============================================================================
92 begin
93 sel <= s1 & s0; -- concatenate s1
and s0
94 with sel
select
95 output <= in0
when "00",
96 in1
when "01",
97 in2
when "10",
98 in3
when "11",
99 'X' when others;
100
101 end with_example;
102
103 -- =============================================================================
104 -- =============================================================================
105 architecture when_example
of mux4_1
is
106
107 -- =============================================================================
108 begin
109
110 output <= in0
when (s1 & s0) =
"00" else
111 in1
when (s1 & s0) =
"01" else
112 in2
when (s1 & s0) =
"10" else
113 in3
when (s1 & s0) =
"11" else
114 'X';
115
116 end when_example;
转载于:https://www.cnblogs.com/shangdawei/archive/2012/05/12/2497528.html
