1 module srl16e_fifo ( clk, datain, wr, dataout, rd, fullness);
2 parameter WIDTH =
8;
3
4 input clk;
5 input [WIDTH-
1:
0] datain;
6 input wr;
7 output [WIDTH-
1:
0] dataout;
8 input rd;
9 output reg [
4:
0] fullness;
10
11 always @(
posedge clk)
12 begin
13 fullness <= (fullness + wr -
rd);
14 end
15 wire [
3:
0] readaddr = (fullness -
1);
16
17 genvar i;
18
19 generate
20 for (i =
0; i < WIDTH; i=i+
1)
begin : srl16
21 SRL16E fifo16(
22 .CLK(clk),
23 .CE(wr),
24 .D(datain[i]),
25 .A0(readaddr[
0]),
26 .A1(readaddr[
1]),
27 .A2(readaddr[
2]),
28 .A3(readaddr[
3]),
29 .Q(dataout[i]));
30 end
31 endgenerate
32
33 endmodule
转载于:https://www.cnblogs.com/shangdawei/archive/2012/05/10/2494216.html
相关资源：论文研究-基于SRL16E的PN码生成器的设计 .pdf
